(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of fabricating a single gate having dual work-functions in the fabrication of integrated circuits.
(2) Description of the Prior Art
As technology progresses, enabling higher levels of integration within system integrated circuit chips, it will be essential to be able to fabricate semiconductor device gates that accommodate different work-functions within a single gate across a short device channel. Many mature methods can be used to fabricate such gates, either metal or silicon. However, these processes might be cumbersome or expensive.
U.S. Pat. No. 5,770,490 to Frenette et al discloses a dual work-function device wherein different gates have different work-functions depending on doping. U.S. Pat. No. 6,187,657 to Xiang et al shows a gate composed of dual gate materials. U.S. Pat. No. 5,620,906 to Yamaguchi et al teaches ion doping to form source/drain regions. U.S. Pat. No. 5,530,265 to Takemura and U.S. Pat. No. 6,235,574 to Tobben et al show doping processes.
Accordingly, a primary object of the invention is to provide a process for forming a single gate having dual work-functions in the fabrication of integrated circuits.
A further object of the invention is to provide a process for forming a single gate having a dual work-function by means of plasma enhanced ion doping in the fabrication of integrated circuits.
Another object of the invention is to provide a process for forming a single gate having a dual work-function by means of selective plasma enhanced ion doping.
In accordance with the objects of the invention, a method for forming a single gate having a dual work-function is achieved. A gate electrode is formed overlying a gate dielectric layer on a substrate. Sidewalls of the gate electrode are selectively doped whereby the doped sidewalls have a first work-function and whereby a central portion of the gate electrode not doped has a second work-function to complete formation of a single gate having multiple work-functions in the fabrication of integrated circuits.